1. Field of the Invention
This invention relates to a process for fabricating slots of different types in a semiconductor material and, more particularly, relates to a process for fabricating slots of different types in self-aligned relationship
2. Discussion of Background and Prior Art
As the densities of integrated circuits increase, there has been a trend in isolation technology to use trench or slot formation processes for form physical gaps between active regions in lieu of the more conventional pn junction and local-oxidation (LOCOS.TM.) structures. See, e.g., D. N. K. Wang et al, "Reactive-Ion Etching Eases Restrictions on Materials and Feature Sizes", Electronics, Nov. 3, 1983, pp. 157, 159. This trend does not result from the availability of anisotropic etches which produce narrow, deep slots in silicon since these etches do not readily form arbitrary shapes or small feature sizes. See, e.g., D. L. Kendall, "Vertical Etching of Silicon at Very High Aspect Ratios", Annual Review of Material Science, 1979, v. 9, pp. 373-403. The trend results primarily from the availability of physical etching equipment such as plasma etchers or equipment which uses both physical and wet chemical processes such as reactive ion etch equipment. In theory, such equipment employing physical etching mechanisms can etch holes and features of arbitrary shape, e.g., shapes of any type that may be defined in masks of the type employed in semiconductor fabrication.
In addition to the formation of slots in semiconductor wafers for isolating individual devices, slots are also being considered for use as active elements. For example, a slot may be filled with appropriate materials so that it functions as a capacitor, see, e.g. K. Minegishi et al, "A Submicron CMOS Megabit Level Dynamic RAM Technology Using a Doped Face Trench Capacitor Cell", Proceedings IEDM 1983, p. 319. Ultimately it is desired that slots of various types and shapes may be fabricated on the same integrated circuit. For example, an array of isolation slots may be intermixed with an array of active element slots. Or an array of one type of isolation slot may be intermixed with an array of another type of isolation slot. In either case, since many of the same process steps will be used for forming both types of slots even though the end use or specifications are different, it would be desirable to use the same mask for each type of slot, preferably in self-aligned fashion. The desirability of self-aligned processes and the various techniques for achieving self-alignment have been well developed in the semiconductor processing art. See, e.g., I. E. Magdo et al, "Self-Aligned ROI to SAM Structure", IBM Technical Disclosure Bull., v. 24, No. 10, pp. 5115-18, March 1982; and P. W. Betz et al, "Self-Aligned Contact Holes", IBM Technical Disclosure Bull., v. 24, No. 9, pp. 4643-4, February 1982. In S. D. Malaviya, "Self-Aligned Deep Trench Isolation for Bipolar Transistors", IBM Technical Disclosure Bull., v. 25, No. 5, pp. 2292-3, October 1982 a process is shown for fabricating slots or trenches which are self-aligned to adjacent active areas. There is no disclosure of multiple types of slots or of self-alignment between slots.
In order to use a single mask for forming different circuit features it is known to use selective etches. The use of a single mask for forming different circuit features is becoming more common due to the increasing complexity of devices. For example, when integrated circuits were based on simpler structures one could use separate mask sets for most of the layers in sequence. However, as structures have become progressively more complex it has become necessary to use other means in addition to separate masks to produce structural features. Separate masks and the associated processing steps reduce yield and add to the cost of processing and are therefore to be avoided, if possible. One of these additional means has been the aforementioned use of selective etching. By selective etching is meant an etch which etches one material preferentially to another material. Various etches which have selective etching properties with respect to the several semiconductor materials, e.g., silicon nitride, silicon dioxide, silicon, aluminum alloys, etc., are known in the art. See, e.g., D. N. K. Wang et al, "Reactive-ion etching eases restrictions on materials and feature sizes", Electronics, Nov. 3, 1983, p. 157 ; and L. M. Ephrath, "Reactive Ion Etching for VLSI", IEEE Transactions on Electron Devices, v. ED-28, No. 11, November 1981, p. 1315.